A semiconductor memory is taught in WO 02/054405 A2. The semiconductor memory disclosed therein has first lines (bit lines) whose line path incorporates transistors which are not selection transistors for memory cells but rather, as part of the bit line, are used for electrically disconnecting a subsection of the respective bit line, depending on the switching state, and hence shortening the bit line length electrically.
Such shortening of the bit line length by means of circuitry can be used to reduce the power consumption of the semiconductor circuit. Whenever a memory cell which is connected to a bit line (or to a word line) is read or refreshed, the charge stored in the memory cell, for example in its capacitor, is passed to the open bit line, which alters the slatter's electrical potential. The change in potential is read using a signal amplifier and is interpreted as a digital zero or one. Potential thresholds are stipulated, above or below which the respective digital data value is assigned to the potential, which has been read.
The greater the length of the bit line, the higher the charge that needs to be applied for storage in the memory cells, which charge is required for sufficiently reliable reading of the digital information. In this context, particularly in the case of volatile semiconductor memories, it should be remembered that the memory cells lose a portion of their charge after a short time, i.e., are continuously discharging, and therefore need to be refreshed at regular, sufficiently short intervals of time. Hence, when a memory cell connected to a bit line is read, only a portion of the originally stored charge is read. Refreshing, i.e., regularly reading and overwriting the memory cells, involves a larger quantity of charge being written back to the memory cell. These charge reversal operations, which respectively extend over one bit line, result in a power consumption which, particularly in the case of mobile appliances, which contain the semiconductor memories mentioned at the outset, shortens the period of use independent of the mains.
To lower the power consumption, it is possible, particularly in semiconductor memories for mobile appliances, to provide shorter bit lines or a combination of shorter and longer bit lines in a memory cell area; in this case, however, larger numbers of bit lines and therefore also more signal amplifiers are needed for the same number of memory cells, which increases the area taken up for each memory cell.
DE 101 14 280 A1 (corresponding U.S. Pat. No. 6,639,862) proposes lowering the power consumption by reusing at least a portion of the quantity of charge transported when a bit line is read, in order to write a charge back to the memory cell during refreshing, for example. To this end, the quantity of charge which is read is buffer-stored. Although this practice reduces the power consumption, the access speed is limited, since it is respectively necessary to read a bit line of full length. In the semiconductor memory known from WO 02/054405 A2 (corresponding U.S. Patent Publication No. 2002/0085405), the transistors incorporated into the center of the bit lines can be used to shorten the bit line length. However, this requires the transistor to be switched beforehand, and this switching operation needs to be interposed between the storage and read operations customary in normal memory operation and therefore slows down memory operation, despite the lower power consumption.
A further drawback of the semiconductor memories described in WO 02/054405 A2 is that the devices or transistors for selectively accessing memory cells exclusively in the region of a shortened bit line half need to be operated at very high reverse voltages if they are intended to block at sufficiently high resistance for both bit values zero and one. A high reverse voltage is necessary because the potential values of 0 V and 1.8 V, for example, which are required for a digital zero and for a digital one are present on both sides of the neutral potential of, by way of example, 0.9 V. Since the transistor needs to be conductive in the off state, only normally on depletion-mode transistors (depletion MOSFETs) are suitable. If the high reverse voltages need to be avoided in order to reduce the power consumption, the devices for selectively actuating subsections need to be produced using combinations of pFET and nFET transistors (p-doped or n-doped field effect transistors); such a circuit takes up additional memory area, however.
Finally, the single transistor used for temporary shortening of the bit line also has an intrinsic capacitance representing an additional parasitic capacitance in addition to the bit line capacitance.
A further drawback is that if memory cells situated between the bit line transistors and the signal amplifiers are to be read only using half of the bit line length, then every change between a memory cell to be read on this side of a bit line transistor and a memory cell to be read on that side of a bit line transistor on the same bit line requires that the bit line transistor change over between the blocking state and the conductive state, i.e., changeover between half of the bit line length and the full bit line length, and vice versa. Hence, all access to a memory cell within the memory cell array first requires a check to determine whether the bit line in question can be shorted using the bit line transistor or has already been shortened.